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Multiplier
Accumulator Component VHDL Implementation |
As
integrated circuit technology has improved to allow more and more components on
a chip, digital systems have continued to grow in complexity. As digital systems
have become more complex, detailed design of the systems at the gate and flip-flop
level has become very tedious and time consuming. For this reason, use of hardware
description languages in the digital design process continues to grow in importance.
A hardware description language allows a digital system to be designed and debugged
at a higher level before conversion to the gate and flip-flop level. Use of synthesis
CAD tools to do this conversion, is becoming more widespread. This is analogous
to writing software programs in a high level language such as C, and then using
a compiler to convert the programs to machine language. The two most popular hardware
description languages are VHDL and Verilog.The
MAC unit provides high-speed multiplication, multiplication with cumulative addition,
multiplication with cumulative subtraction, saturation, and clear-to-zero functions.
These operations are extensively used in Fast Fourier Transforms required by the
MP3 Chip. The 16 bit multiplier accumulator unit is based on the multiplier accumulator
specification of the Analog Devices ADSP2181 chip. Field Programmable Gate Arrays
(FPGAs) are being used increasingly in embedded general purpose computing environments
as performance accelerators. This new use beyond the traditional usage as glue
logic and as a rapid prototyping enabler has also renewed interest in the FPGA
architecture. The fine grain reconfigurability of the FPGA architecture makes
it an ideal candidate for use in system-on-chip environments that strive to integrate
heterogeneous programmable architectures
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